library verilog;
use verilog.vl_types.all;
entity transmit is
    port(
        rateen          : in     vl_logic;
        clk             : in     vl_logic;
        rst             : in     vl_logic;
        iocs            : in     vl_logic;
        iorw            : in     vl_logic;
        data            : in     vl_logic_vector(7 downto 0);
        ioaddr          : in     vl_logic_vector(1 downto 0);
        tbr             : out    vl_logic;
        txd             : out    vl_logic
    );
end transmit;
